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march 2011 doc id 17884 rev 3 1/60 60 stmpe1801 xpander logic? 18-bit enhanced port expand er with keypad controller features 18 gpios configurable as gpi, gpo, keypad matrix, special key or dedicated key function operating voltage: 1.65 - 3.6 v hardware keypad controller (kpc) (10 x 8 matrix with 4 optional dedicated keys maximum) keypad controller capable of detecting keypress in hibernation mode interrupt output (open drain) pin advanced power management system ultra-low standby mode current programmable pull-up resistors for all gpio pins esd performance on gpio pins: ? 8 kv human body model (jesd22 a114-c) esd performance on v cc , gnd, int b , r stb , scl, sda pins: ? 3 kv human body model (jesd22 a114-c) description the stmpe1801 is a gpio (general purpose input/output) port expander capable of interfacing a main digital asic via the two-line bidirectional bus (i 2 c). a separate gpio expander ic is often used in mobile multimed ia platforms to resolve the problem of the limited number of gpios typically available on digital engines. the stmpe1801 offers high flexibility, as each i/o can be configured as input, output, special key, keypad matrix or dedicated key function. this device is designed to include very low quiescent current, and a wakeup feature for each i/o, to optimize the power consumption of the device. potential applications for the stmpe1801 include portable media players, game consoles, mobile and smart phones. flip-chip csp 25 (2.03 x 2.03 mm) table 1. device summary order code package packaging STMPE1801BJR flip-chip csp 25 (2.03 x 2.03 mm) 0.4 mm pitch tape and reel www.st.com
contents stmpe1801 2/60 doc id 17884 rev 3 contents 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.3 gpio pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 input/output dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 10 5 register address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6 i2c specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.1 i2c related pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.2 i2c addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.3 start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.4 stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.5 acknowledge bit (ack) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.6 data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.7 memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.8 operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.9 general call address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7 system controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.1 system level registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.2 states of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.2.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . auto-hibernate 20 7.2.2 . . . . . . . . . . . . . . . . . . . . . . . . keypress detect in the hibernate mode 21
stmpe1801 contents doc id 17884 rev 3 3/60 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . clocking system 22 8.0.1 clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.0.2 power mode programming sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9 interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.1 interrupt system register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9.2 interrupt latency for the gpio hot keys . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9.3 programming sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 10 gpio controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 10.1 gpio control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10.1.1 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10.2 hotkey feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 10.2.1 programming sequence for hotkey . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 10.2.2 minimum pulse width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 11 keypad controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 11.1 keypad configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 11.2 keypad controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 11.3 data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 11.4 keypad combination key registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 11.5 using the keypad controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 11.5.1 ghost key handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 11.5.2 key detection priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 11.5.3 keypad wakeup from hibernate mode . . . . . . . . . . . . . . . . . . . . . . . . . . 52 11.5.4 keypad controller combination key interrupt . . . . . . . . . . . . . . . . . . . . . 52 12 miscellaneous features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 12.1 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 13 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
block diagram stmpe1801 4/60 doc id 17884 rev 3 1 block diagram figure 1. stmpe1801 block diagram +eypadcontroller -ain&3- 07- '0)/control 3#, 3$! ).4" 234" -58 0/2 )# )nterface 6 ## +eypadoutput #/, #/, '0)/ +eypadinput 2/7 2/7 '0)/ -58 '.$
stmpe1801 pin settings doc id 17884 rev 3 5/60 2 pin settings 2.1 pin connection figure 2. pin connection (top-through view) 2.2 pin description rstb _ gpio _ 14 gpio9 gpio2 gpio7 gpio15 gpio10 nc gpio6 sda gpio16 gpio1 gpio17 gpio0 gpio4 intb gnd gpio1 3 gpio8 gpio3 ! " # $ % !-6 vcc gpio11 gpio5 scl gpio12 flip-cip csp 25 tale 2 pin description pin numer type symol name and unction d4 i/o gpio0 gpio0/row0 c4 i/o gpio1 gpio1/row1 a4 i/o gpio2 gpio2/row2 e5 i/o gpio3 gpio3/row3 d5 i/o gpio4 gpio4/row4 c5 i/o gpio5 gpio5/row5 b5 i/o gpio6 gpio6/row6 a5 i/o gpio7 gpio7/row7 e4 i/o gpio8 gpio8/col0 a3 i/o gpio9 gpio9/col1 b3 i/o gpio10 gpio10/col2
pin settings stmpe1801 6/60 doc id 17884 rev 3 2.3 gpio pin functions c3 i/o gpio11 gpio11/col3 d3 i/o gpio12 gpio12/col4 e3 i/o gpio13 gpio13/col5 a2 i/o gpio14 gpio14/col6 b2 i/o gpio15 gpio15/col7 c2 i/o gpio16 gpio16/col8 d2 i/o gpio17 gpio17/col9 e1 o intb open drain interrupt output pin. programmable active low (a pull-up resistor is required) or active high (a pull-down resistor is required). fail safe. pull to v cc if not in use. a1 i rstb external reset input. active low. fail safe. reset pulse width must be more than 500 s to be valid. c1 a sda i 2 c data. fail safe d1 a scl i 2 c clock. fail safe b4 - nc no connect b1 - v cc power supply e2 - gnd ground table 2. pin description (continued) pin number type symbol name and function table 3. gpio pin function name primary function alternate function gpio0 gpio keypad row 0 gpio1 gpio keypad row 1 gpio2 gpio keypad row 2 gpio3 gpio keypad row 3 gpio4 gpio keypad row 4 gpio5 gpio keypad row 5 gpio6 gpio keypad row 6 gpio7 gpio keypad row 7 gpio8 gpio keypad column 0 gpio9 gpio keypad column 1 gpio10 gpio keypad column 2 gpio11 gpio keypad column 3 gpio12 gpio keypad column 4
stmpe1801 pin settings doc id 17884 rev 3 7/60 the default function is always gpio. as soon as the key scanning is enabled through the keypad registers, the function is then switched to the key function and then any configuration made in the gpio registers is ignored. gpio13 gpio keypad column 5 gpio14 gpio keypad column 6 gpio15 gpio keypad column 7 gpio16 gpio keypad column 8 gpio17 gpio keypad column 9 table 3. gpio pin function name primary function alternate function
maximum ratings stmpe1801 8/60 doc id 17884 rev 3 3 maximum ratings stressing the device above the rating listed in the ?absolute maximum ratings? table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not imp lied. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. 3.1 absolute maximum ratings 3.2 thermal data table 4. absolute maximum ratings symbol parameter value unit v cc supply voltage 4.5 v v in input voltage on gpio pin 4.5 v v esd minimum esd protection on each gpio pin (hbm model - jesd22 a114-c ) 8 kv v esd esd protection on other pins (hbm model - jesd22 a114-c ) 3 kv table 5. thermal data symbol parameter min typ max unit r thja thermal resistance junction-ambient ? 100 ? c/w t a operating ambient temperature -40 25 85 c t j operating junction temperature -40 25 125 c
stmpe1801 electrical specification doc id 17884 rev 3 9/60 4 electrical specification 4.1 dc electrical characteristics table 6. dc electrical characteristics symbol parameter test conditions value unit min typ max v cc supply voltage - 1.65 ? 3.6 v i cc active current (core and analog) - 1 key press 1.8 v ? 28 55 a 3.3 v ? 90 140 a i hibernate hibernate current 1.8 v 25 c ?? 0.5 a 85 c ?? 1 3.3 v 25 c ?? 0.5 a 85 c ?? 1 i ntb open drain output current v ol(max) =0.45 v at v cc =1.8 v v ol(max) =0.83 v at v cc =3.3 v ? 4 ? ma
electrical specification stmpe1801 10/60 doc id 17884 rev 3 4.2 input/output dc electrical characteristics table 7. i/o dc electrical characteristics symbol parameter test conditions value unit min typ max v il low level input voltage v cc = 1.8 v ?? 0.2 v cc v v cc = 3.3 v ?? 0.2 v cc v ih high level input voltage v cc = 1.8 v 0.8 v cc ?? v v cc = 3.3 v 0.8 v cc ?? v hyst schmitt trigger hysteresis v cc = 1.8 v ? 0.10 ? v v cc = 3.3 v ? 0.20 ? v ol low level output voltage i ol = 4 ma, v cc = 1.8 v ?? 0.45 v i ol = 4 ma, v cc = 3.3 v ?? 0.45 v oh high level output voltage i oh = -4 ma, v cc = 1.8 v 1.35 ?? v i oh = -4 ma, v cc = 3.3 v 2.48 ?? r up equivalent pull-up resistance v cc = 3.3 v. active implementation, r value is determined by the current measured at 0 v 30 60 90 k v cc = 1.8 v. active implementation, r value is determined by the current measured at 0 v 50 100 150
stmpe1801 register address doc id 17884 rev 3 11/60 5 register address table 8. stmpe1801 register summary table addres s register name description auto- increment 76543210 00 chip_id chip identification no 8-bit chip id 01 version_id version identification no 8-bit version id 02 sys_ctrl system control no sf_ rst reserved gpi _db 1 gpi _db 0 rsv d 04 int_ctrl_low interrupt control ye s reserved ic2 ic1 ic0 05 int_ctrl_high reserved 06 int_en_mask_low interrupt enable mask ye s reserved ie4 ie3 ie2 ie1 ie0 07 int_en_mask_high reserved 08 int_sta_low interrupt status yes reserved ie4 ie3 ie2 ie1 ie0 09 int_sta_high reserved 0a int_en_gpio_mask _low interrupt enable gpio mask ye s ieg 7 ieg 6 ieg 5 ieg 4 ieg 3 ieg 2 ieg 1 ieg 0 0b int_en_gpio_mask _mid ieg 15 ieg 14 ieg 13 ieg 12 ieg 11 ieg 10 ieg 9 ieg 8 0c int_en_gpio_mask _high reserved ieg 17 ieg 16 0d int_sta_gpio_low interrupt status gpio ye s isg 7 isg 6 isg 5 isg 4 isg 3 isg 2 isg 1 isg 0 0e int_sta_gpio_mid isg 15 isg 14 isg 13 isg 12 isg 11 isg 10 isg 9 isg 8 0f int_sta_gpio_high reserved isg 17 isg 16 10 gpio_set_low gpio set pin state ye s io7 io6 io5 io4 io3 io2 io1 io0 11 gpio_set_mid io15 io14 io13 io12 io11 io10 io9 io8 12 gpio_set_high reserved io17 io16 13 gpio_clr_low gpio clear pin state ye s io7 io6 io5 io4 io3 io2 io1 io0 14 gpio_clr_mid io15 io14 io13 io12 io11 io10 io9 io8 15 gpio_clr_high reserved io17 io16 16 gpio_mp_low gpio monitor pin state ye s io7 io6 io5 io4 io3 io2 io1 io0 17 gpio_mp_mid io15 io14 io13 io12 io11 io10 io9 io8 18 gpio_mp_high reserved io17 io16
register address stmpe1801 12/60 doc id 17884 rev 3 19 gpio_set_dir_low gpio set pin direction register ye s io7 io6 io5 io4 io3 io2 io1 io0 1a gpio_set_dir_mid io15 io14 io13 io12 io11 io10 io9 io8 1b gpio_set_dir_hig h reserved io17 io16 1c gpio_re_low gpio rising edge ye s io7 io6 io5 io4 io3 io2 io1 io0 1d gpio_re_mid io15 io14 io13 io12 io11 io10 io9 io8 1e gpio_re_high reserved io17 io16 1f gpio_fe_low gpio falling edge ye s io7 io6 io5 io4 io3 io2 io1 io0 20 gpio_fe_mid io15 io14 io13 io12 io11 io10 io9 io8 21 gpio_fe_high reserved io17 io16 22 gpio_pull_up_lo w gpio pull up yes io7 io6 io5 io4 io3 io2 io1 io0 23 gpio_pull_up_mid io15 io14 io13 io12 io11 io10 io9 io8 24 gpio_pull_up_hig h reserved io17 io16 30 kpc_row keypad row scanning ye s ro w7 ro w6 ro w5 ro w4 ro w3 ro w2 ro w1 ro w0 31 kpc_col_low keypad column scanning ye s col 7 col 6 col 5 col 4 col 3 col 2 col 1 col 0 32 kpc_col_high reserved col 9 col 8 33 kpc_ctrl_low key config: scan count and dedicated key ye s scan_count 0-3 dkey 0-3 34 kpc_ctrl_mid db6 db5 db4 db3 db2 db1 db0 rsv d 35 kpc_ctrl_high rsv d cm b_k ey reserved scan_fr eq 36 kpc_cmd keypad command yes reserved kpc _lc k sca n 37 kpc_comb_key_0 keypad combination key mask ye s c4 c3 c2 c1 c0 r2 r1 r0 38 kpc_comb_key_1 c4 c3 c2 c1 c0 r2 r1 r0 39 kpc_comb_key_2 c4 c3 c2 c1 c0 r2 r1 r0 table 8. stmpe1801 register summary table addres s register name description auto- increment 76543210
stmpe1801 register address doc id 17884 rev 3 13/60 3a kpc_data_byte0 keypad data yes up/ dw n c3 c2 c1 c0 r2 r1 r0 3b kpc_data_byte1 up/ dw n c3 c2 c1 c0 r2 r1 r0 3c kpc_data_byte2 up/ dw n c3 c2 c1 c0 r2 r1 r0 3d kpc_data_byte3 sf7 sf6 sf5 sf4 sf3 sf2 sf1 sf0 3e kpc_data_byte4 reserved dedicated key 0 - 3 table 8. stmpe1801 register summary table addres s register name description auto- increment 76543210
i2c specification stmpe1801 14/60 doc id 17884 rev 3 6 i 2 c specification the features supported by the i 2 c interface are listed below: i 2 c slave device operates at v cc (1.8 - 3.6 v) compliant to philips i 2 c specification version 2.1 supports standard (up to 100 kbps) and fast (up to 400 kbps) modes 7-bit device addressing modes general call start/restart/stop 6.1 i 2 c related pins scl sda the device supports both 1.8 v i 2 c and 3.3 v i 2 c operations. it is recommended that vpullup at scl and sda externally is greater or equal to v cc . 6.2 i 2 c addressing the stmpe1801 7-bit addressing is set to 40h. 6.3 start condition a start condition is iden tified by a falling edge of sda while scl is stable at high state. a start condition must precede any data/command transfer. the device continuously monitors for a start condition and does not respond to any transaction unless one is encountered. the first byte is scanned after the start command is detected to check for device id. ensure that all state machines are fl ushed when start instruction is issued. 6.4 stop condition a stop condition is identified by a rising edge of sda while scl is stable at high state. a stop condition terminates the communication between the slave device and bus master. a read command that is followed by noack can be followed by a stop condition to force the slave device into idle mode. when the slave device is in idle mode, it is ready to receive the next i 2 c transaction. a stop condition at the end of a write command stops the write operation to the registers. once the stop condition is detected, the device should release the bus and go to hibernate mode if there is no more activity. an i 2 c transaction with a start bit followed immediately by a stop condition should not cause any i 2 c lock-up.
stmpe1801 i2c specification doc id 17884 rev 3 15/60 6.5 acknowledge bit (ack) the acknowledge bit is used to indicate a successful byte transfer. the bus transmitter releases the sda after sending eight bits of data . during the ninth bit, the receiver pulls the sda low to acknowledge the receipt of the eight bits of data. the receiver may leave the sda in high state if it does not acknowledge the receipt of the data. 6.6 data input the device samples the data input on sda on the rising edge of the scl. the sda signal must be stable during the rising edge of scl and the sda signal must change only when scl is driven low. 6.7 memory addressing for the bus master to communicate to the slave device, the bus master must initiate a start condition and be followed by the slave device address. accompanying the slave device address, there is a read/write bit (r/w ). the bit is set to 1 for read and 0 for write operation. if a match occurs on the slave device address, the corresponding device gives an acknowledgement on the sda during the 9th bit time. if there is no match, it deselects itself from the bus by not responding to the transaction. 6.8 operation modes table 9. operating modes mode byte programming sequence read 1 start, device address, r/w =0, register address to be read restart, device address, r/w =1, data read, stop if no stop is issued, the data read can be continuously performed. if the register address falls within the range that allows address auto- increment, then register address auto-increments internally after every byte of data being read. for register address that fails within a non- incremental address range, the addre ss is kept static throughout the entire read operation. refer to table 8.: stmpe1801 register summary table for the address ranges that are auto-increment and non-increment. an example of such a non-increment address is fifo.
i2c specification stmpe1801 16/60 doc id 17884 rev 3 figure 3. operating modes write 1 start, device address, r/w =0, register address to be written, data write, stop if no stop is issued, the data write can be continuously performed. if the register address falls within the range that allows address auto- increment, then register address auto-increment internally after every byte of data being written. for those register addresses that fall within a non-incremental address range, the address will be kept static throughout the entire write operation. refer to table 8.: stmpe1801 register summary table for the address ranges t hat are auto-increment and non-increment. an example of a non-increment address is data port for initializing the pwm. table 9. operating modes mode byte programming sequence one byte re ad start rnw=0 ack ack restart rnw=1 ack noack stop more than one byte re ad start rnw=0 ack ack restart rnw=1 ack ack ack noack stop one byte write start rnw=0 ack ack ack stop m ore th an one byte write start rnw=0 ack ack ack ack ack stop master slave dev addr reg addr dev addr data read data read + 2 dev addr reg addr data to be written dev addr reg addr dev addr data read data to write + 1 data to write + 2 dev addr reg addr data to write data read + 1
stmpe1801 i2c specification doc id 17884 rev 3 17/60 6.9 general call address a general call address is a transaction with the slave address of 0x00 and r/w =0. when a general call address is asserted, the stmpe1801 responds to this transaction with an acknowledgement and behaves as a slave-receiver mode. the meaning of a general call address is defined in the second byte sent by the master-transmitter. note: all other second byte values are ignored. table 10. general call address r/w second byte value definition 0 0x06 a 2-byte transaction in which the second byte tells the slave device to reset and write (or latch in) the 2-bit programmable part of the slave address. 0 0x00 not allowed as second byte.
system controller stmpe1801 18/60 doc id 17884 rev 3 7 system controller 7.1 system level registers the system controller is the heart of the stmpe1801. it contains the registers for power control and chip identification. the system registers are: chip_id chip identi fication register version_id version iden tification register address register name 00 chip_id 01 version_id 02 sys_ctrl 76543 2 1 0 8-bit chip_id rrrrr r r r 11000 0 0 1 76543 2 1 0 8-bit version_id rrrrr r r r 00010 0 0 0
stmpe1801 system controller doc id 17884 rev 3 19/60 sys_ctrl system control register address: 02 type: r/w reset: 0x06 description: system control register. 76543 2 1 0 sf_rst reserved gpi_db1 gpi_db0 rsvd wrrrr rw rw r 00000 1 1 0 [7] sf_rst: soft reset writing a ?1? to this bit will do a soft reset of the device. once the reset is done, this bit is cleared to ?0? by the hw. [6:3] reserved [2:1] gpi_db [1:0] gpi [17:0] operati onal mode de-bounce time ?00? = 30 s ?01? = 90 s ?10? = 150 s ?11? = 210 s (default) [0] reserved
system controller stmpe1801 20/60 doc id 17884 rev 3 7.2 states of operation figure 4. states of operation the device has two main modes of operation: operational mode: this is the mode, whereby normal operation of the device takes place. in this mode, the main finite state machine (fsm) unit routes 32 khz clock to all the device blocks. hibernate mode: this mode is entered automatically in auto-hibernate mode. when the device is in hibernate mode, the 32 khz cloc k is disabled. if there is a keypad activity, interrupt event, hotkey activity or i 2 c transaction, the device switches to operational mode. a reset event brings back the system to operational mode. 7.2.1 auto-hibernate the stmpe1801 is set to go into hibernate mode automatically if there is a period of inactivity (~ 100 s) following the completion of i 2 c transaction with the host. the stmpe1801 will continue counting down for hiber nation mode activation even if there is an i 2 c transaction sent by the host to other slave devices. any i 2 c transaction from the host to the stmpe1801 resets the hibernate counter. auto-hibernate mode occurs only when all the keys are released and fifo is emptied through reading. this is to prevent any loss of data. the hibernate mode counter should start when any of the following conditions is detected: ? once the i 2 c transaction is comp leted or a stop condition is detected. ? if the device id in the i 2 c transaction is invalid. when there is a keypad activity, the device should go into hibernate mode only when all the previously pressed keys are released. am04176v1 hi b ern a te 3 2 khz: off o per a tion a l 3 2 khz: on no a ctivity ( ~ 100 s ) keyp a d, interr u pt s & i 2 c tr a n sa ction ( ~ 4 8 s ) re s et
stmpe1801 system controller doc id 17884 rev 3 21/60 any keypad activity, interrupt event, hotkey activity or valid i 2 c transaction wakes up the device from hibernate mode and switches to operational mode automatically. 7.2.2 keypress detect in the hibernate mode when in hibernate mode, any keypress detected causes the system to go into operational mode (~48 s) . the system will then de-bounce the key to detect a valid key. if the keypress detected is valid, the system stays in operation mode. if the key detected is invalid, the system goes back into hibernate mode.
clocking system stmpe1801 22/60 doc id 17884 rev 3 8 clocking system in order to reduce the power consumption, the stmpe1801 tu rns off the oscillator during hibernate mode. figure 5. clocking system 8.0.1 clock source by default, when the stmpe1801 powers up, it derives a 32 khz clock from the internal rc oscillator for its operation. there are 4 sources of reset: rstb pin low voltage detect (lvd) reset soft reset bit of th e sys_ctrl register i 2 c reset from the i 2 c block. !-6 3ystemclock #lockcontrol k(z /3# 3#,pin
stmpe1801 clocking system doc id 17884 rev 3 23/60 8.0.2 power mode programming sequence the device enters auto hibernate mode when there is inactivity for a fixed period of time. to wake up the device, the host is required to: ? send an i 2 c transaction to the device. to do a soft reset to the device, the host needs to do the following: ? write a '1' to bit 7 of the sys_ctrl register. this bit is automatically cleared upon reset. to come out of the hibernate mode, the following needs to be done by the host: ? assert a system reset ? or put a wakeup on the i 2 c transaction ? interrupt activity
interrupt system stmpe1801 24/60 doc id 17884 rev 3 9 interrupt system the stmpe1801 uses a highly flexible interrupt system. it allows the host system to configure the type of system events that should result in an interrupt, and pinpoints the source of interrupt by status registers. the int pin can be configured as active high (a pull- down resistor is required), or ac tive low (a pull-up resistor is required). if int pin is not in use, it is necessary to pull int pin to v cc . once asserted, the int pin would de-assert when a read is done to the corresponding bit either in the int_sta register or int_sta_gpio register. figure 6. interrupt system !-6 +eypad controller '0)/ controller )nterrupt enable '0)/ register )nterruptstatus register )nterruptenable register )nterrupt generation )nterruptpolaritycontrol 3ystemcontrolregister
stmpe1801 interrupt system doc id 17884 rev 3 25/60 9.1 interrupt syste m register map 9.2 interrupt latency for the gpio hot keys when the generation of interrupts by the gpio as input is enabled for the hot keys, the latency (time taken from actual transition at gpio to time of int pin assertion) is shown in the following table: table 11. interrupt system register map address register name description auto-increment (during sequential r/w) 04 int_ctrl_low interrupt control register ye s 05 int_ctrl_high yes 06 int_en_mask_low interrupt enable mask register ye s 07 int_en_mask_high yes 08 int_sta_low interrupt status register ye s 09 int_sta_high yes 0a int_en_gpio_mask_low interrupt enable gpio mask register ye s 0b int_en_gpio_mask_mid yes 0c int_en_gpio_mask_high yes 0d int_sta_gpio_low interrupt status gpio register ye s 0e int_sta_gpio_mid yes 0f int_sta_gpio_high yes table 12. gpio hot keys interrupt latency state of operation interrupt latency comments hibernation > 200 s (default) latency can be programmed by the gpi_db bits of sys_ctrl register active > 200 s (default)
interrupt system stmpe1801 26/60 doc id 17884 rev 3 int_ctrl interrupt control register address: 04, 05 type: r, r/w reset: 0x00 description: the interrupt control register is used to configure the interrupt controller. it has global enable interrupt mask bit that controls the interruption to the host. 1514131211109876543 2 1 0 int_ctrl_high int_ctrl_low reserved ic2 ic1 ic0 rrrrrrrrrrrrrrwrwrw [15:3] reserved [2] ic2: output interrupt polarity ?0? = active low/falling edge ?1? = active high/rising edge [1] ic1: output interrupt type ?0? = level interrupt ?1? = edge interrupt (pulse width of 200s) [0] ic0: global interrupt mask bit when this bit is written a ?1?, it allows interruption to the host. if it is written with a ?0?, then, it disables all interruption to the host. writing to this bit does not affect the int_en_mask value.
stmpe1801 interrupt system doc id 17884 rev 3 27/60 int_en_mask interrupt enable mask register address: 06, 07 type: r, r/w reset: 0x00 description: the interrupt enable mask register is used to enable the interruption from a particular interrupt source to the host. 1514131211109876543 2 1 0 int_en_mask_high int_en_mask_low reserved ie4 ie3 ie2 ie1 ie0 rrrrrrrrrrrrwrwrwrwrw 0000000000000 0 0 0 [15:4] reserved [4:0] ie[x]: interrupt enable mask (where x = 3 to 0) ie0: default value is 0. ie1: keypad controller interrupt mask ie2: keypad controller fifo overflow interrupt mask ie3: gpio controller interrupt mask ie4: combination key interrupt enable writing a ?1? to the ie[x] bit enables the interruption to the host.
interrupt system stmpe1801 28/60 doc id 17884 rev 3 int_sta interrupt status register address: 08, 09 type: r reset: 0x00 description: the interrupt status register monitors the status of the interruption from a particular interrupt source to the host. the int_sta bits are constantly updated regardless whether the int_en bits are enabled or not. 1514131211109876543210 int_sta_high int_sta _low reserved is4 is3 is2 is1 is0 rrrrrr rrrrrrrrrr 000000 0000000001 [15:4] reserved [4:0] is[x] interrupt status (where x = 3 to 0) read: is0: wake-up interrupt status is1: keypad controller interrupt status is2: keypad controller fifo overflow interrupt status is3: gpio controlle r interrupt status is4: combination key interrupt status reading the int_sta register clears all interrupt status bits to ?0? which had been set to ?1? prior to the read event.
stmpe1801 interrupt system doc id 17884 rev 3 29/60 int_en_gpio_mask interrupt enabled gpio mask register address: 0a, 0b, 0c type: r/w reset: 0x00 description: the interrupt enable gpio mask register is used to enable the interruption from a particular gpio interrupt source to the host. the ieg[17:0] bits are the interrupt enable mask bits correspond to the gpio[17:0] pins. 76543 2 1 0 int_en_gpio_mask_low ieg7 ieg6 ieg5 ieg4 ieg3 ieg2 ieg1 ieg0 rw rw rw rw rw rw rw rw 00000 0 0 0 15 14 13 12 11 10 9 8 int_en_gpio_mask_mid ieg15 ieg14 ieg13 ieg12 ieg11 ieg10 ieg9 ieg8 rw rw rw rw rw rw rw rw 00000 0 0 0 23 22 21 20 19 18 17 16 int_en_gpio_mask_high reserved ieg17 ieg16 r r r r r r rw rw 00000 0 0 0 [17:0 ieg[x]: interrupt enable gpio mask (where x = 17 to 0) writing a ?1? to the ieg[x] bit enables the interruption to the host.
interrupt system stmpe1801 30/60 doc id 17884 rev 3 nt_sta_gpio interrupt status gpio register address: 0d, 0e, 0f type: r reset: 0x00 description: the interrupt status gpio register monitors the status of the interruption from a particular gpio pin interrupt source to the host. the int_sta_gpio bits are constantly updated regardless whether the int_en_gpio_mask bits are enabled or not. the isg[17:0] bits are the interrupt status bits correspond to the gpio[17:0] pins. 76543 2 1 0 int_sta_gpio_low isg7 isg6 isg5 isg4 isg3 isg2 isg1 isg0 rrrrr r r r 00000 0 0 0 15 14 13 12 11 10 9 8 int_sta_gpio_mid isg15 isg14 isg13 isg12 isg11 isg10 isg9 isg8 rrrrr r r r 00000 0 0 0 23 22 21 20 19 18 17 16 int_sta_gpio_high reserved isg17 isg16 rrrrr r r r 00000 0 0 0 [17:0 isg[x] interrupt status gpio (where x = 17 to 0) isg[x] will be set to ?1? if an interrupt is detected on the corresponding gpio pin. reading the int_sta_gpio register clears all interrupt status gpio bits to ?0? which had been set to ?1? prior to the read event.
stmpe1801 interrupt system doc id 17884 rev 3 31/60 9.3 programming sequence to configure and initialize the interrupt controller to allow interruption to host, observe the following steps: 1. set the int_en_mask and int_en_gpio_mask registers to the desired values to enable the interrupt sources that are to be expected to receive from. 2. configure the output interrupt type and polarity and enable the global interrupt mask by writing to the int_ctrl. 3. wait for interrupt. 4. upon receiving an interrupt, the corresponding int bit is asserted. 5. the host comes to read the int_sta register through the i 2 c interface. a ?1? in the int_sta bits indicates that the corresponding interrupt source is triggered. 6. if the is3 bit in int_sta register is set, the interrupt is coming from the gpio controller. then, a subsequent read is performed on the int_sta_gpio register to obtain the interrupt status of all 18 gpios to locate the gpio that triggers the interrupt. this is a ?hot key? feature. 7. after obtaining the interrupt source that triggers the interrupt, the host performs the necessary processing and operations related to the interrupt source. 8. all is[x] bits in int_sta register and isg[x] bits in int_sta_gpio register which are set to ?1? prior to the read event are cleared to ?0? automatically once the reading of the registers are completed. 9. any interrupt inputs received between reading and auto clearing of the registers are kept in a shadow register and updated into the int_sta and int_sta_gpio registers once the auto clearing is completed. 10. once the interrupt is cleared, the int pin is also de-asserted if the interrupt type is level interrupt. an edge interrupt only asserts a pulse width of 200 s. 11. when the interrupt function is no longer required, the ic0 bit in int_ctrl may be set to ?0? to disable the global interrupt mask bit.
gpio controller stmpe1801 32/60 doc id 17884 rev 3 10 gpio controller a total of 18 gpios are available in the stmpe1801 port expander device. most of the gpios are sharing physical pins with alternate functions. the gpio controller contains the registers that allow the host system to configure each of the pins into either a gpio, or one of the alternate functions. unused gpios should be configured as outputs to minimize the power consumption. table 13. gpio controller registers address register name description auto-increment (during sequential r/w) 10 gpio_set_low gpio set pin state register ye s 11 gpio_set_mid yes 12 gpio_set_high yes 13 gpio_clr_low gpio clear pin state register ye s 14 gpio_clr_mid yes 15 gpio_clr_high yes 16 gpio_mp_low gpio monitor pin state register ye s 17 gpio_mp_mid yes 18 gpio_mp_high yes 19 gpio_set_dir_low gpio set pin direction register ye s 1a gpio_set_dir_mid yes 1b gpio_set_dir_high yes 1c gpio_re_low gpio rising edge register ye s 1d gpio_re_mid yes 1e gpio_re_high yes 1f gpio_fe_low gpio falling edge register ye s 20 gpio_fe_mid yes 21 gpio_fe_high yes 22 gpio_pull_up_low gpio pull up register ye s 23 gpio_pull_up_mid yes 24 gpio_pull_up_high yes
stmpe1801 gpio controller doc id 17884 rev 3 33/60 10.1 gpio control registers a group of registers is used to control the exact function of each of the 18 gpios. all the gpio registers are named as gpio_xxx_yyy, where: ? xxx represents the functional group ? yyy represents the byte position of the gpio (low/mid/high) ? low registers control gpio[7:0] ? mid registers control gpio[8:15] ? high registers control gpio[17:16] 10.1.1 bit description the function of each bit is shown in the following table: 76543 2 1 0 gpio_xxx_high reserved io-16 io-17 gpio_xxx_mid io-15 io-14 io-13 io-12 io-11 io-10 io-9 io-8 gpio_xxx_low io-7 io-6 io-5 io-4 io-3 io-2 io-1 io-0 register name description function gpio_mp_yyy gpio monitor pin state reading this bit yields the curr ent state of the bit. writing has no effect. gpio_set_yyy gpio set pin state writing ?1? to this bit causes the corresponding gpio to go to ?1? state. writing ?0? has no effect. gpio_clr_yyy gpio clear pin state writing ?1? to this bit causes the corresponding gpio to go to ?0? state. writing ?0? has no effect. gpio_set_dir_yyy gpio set pin direction ?0? sets the corresponding gpio to input state, and ?1? sets it to output state. gpio_re_yyy gpio rising edge set to ?1? enable rising edge detection on the corresponding gpio. gpio_fe_yyy gpio falling edge set to ?1? enable falling edge detection on the corresponding gpio. gpio_pull_up_yyy gpio pull up set to ?1? enable internal pull-up resistor.
gpio controller stmpe1801 34/60 doc id 17884 rev 3 10.2 hotkey feature a gpio is known as ?hotkey? when it is configured to trigger an interruption to the host whenever the gpio input is being asserted. this feature is applicable in operational mode as well as in hibernate mode. 10.2.1 programming sequence for hotkey 1. configure the gpio pin into input direction by setting the corresponding bit in the gpio set pin direction registers [gpio_set_dir_yyy]. 2. set the gpio rising edge registers [g pio_re_yyy] and gpio falling edge registers [gpio_fe_yyy] to the desire d values to enable the ri sing edge or falling edge detection. 3. configure and enable the interrupt controller to allow the interruption to the host. 4. now, the gpio expander may enter hibernate mode if there is no activity. 5. upon any hot-key being asserted, the device will wake up and issue an interrupt to the host. below are the conditions to be fulfilled in order to configure a hot key: 1. the pin is configured into gpio mode and as input pin. 2. the global interrupt mask bit is enabled. 3. the corresponding gpio interrupt mask bit is enabled. 10.2.2 minimum pulse width the minimum pulse width of the assertion of the hotkey is dependent on the de-bounce time configured. it must be greater than the de-bounce value configured. any pulse width less than the stated value may not be registered.
stmpe1801 keypad controller doc id 17884 rev 3 35/60 11 keypad controller the keypad controller consists of: ? 4 dedicated key controllers that support up to 4 simultaneous dedicated key presses; ? a keyscan controller support a maximum of 10 x 8 key matrix with detection of three simultaneous key presses; ? 8 special function key controllers that support up to 8 simultaneous ?special function? key presses. the key detection priority is dedicated, special function and normal keys. four of the row inputs can be configured as dedicated keys through the setting of dkey0~3 bits of the kpc_ctrl register. the normal key matrix size can be configured through the setting of kpc_row and kpc_col registers. the scanning of each individual row input and column output can be enabled or masked to support a key matrix of variable size from 1 x 1 to 10 x 8. it is allowed to have other 8 special function keys incorporated in the key matrix. the operation of the keypad controller is enabled by the scan bit of kpc_ctrl register. every key activity detected is de-bounced for a period set by the db_1~7 bits of kpc_ctrl register before a key press or key release is confirmed and updated into the output fifo. the key data, indicating the key coordinates and its status (up or down), is loaded into the fifo at the end of a specified number of sca nning cycles (set by scan_count0~3 bits of kpc_ctrl_mid register). an interrupt is generated when a new set of key data is loaded. the fifo has a capacity for ten sets of key data. each set of key data consists of 5 bytes of information when any of the four dedicated keys is enabled. it is reduced to 4 bytes when no dedicated key is involved. when the fifo is full before its content is read, an overflow signal is generated while the fifo will continue to ho ld its content but forbid loading of new key data set.
keypad controller stmpe1801 36/60 doc id 17884 rev 3 figure 7. keypad controller the keypad rows enabled by the kpc_row register are normally 'high', with the corresponding input pins pulled up by resistors internally. after reset, all the keypad columns enabled by the kpc_col register are driven 'low' via weak-pull down resistors. the pull- down resistors on the column are weaker than the pull-up resistors on the rows. if a key is pressed, the stronger pull-up drive on the corresponding row overwrites the weaker pull- down drive on the selected column thus allowing the keyscan controller to sense a "high" input on the selected column. once the keyscan controller senses a "high" on the selected column, the output buffer for the selected column drives the line low overwriting the pull-up resistor on the corresponding row. the row that senses the "low" signal enables the key scan controller to decode the key coordinates (its corresponding row number and column number), save the key data into a de-bounce buffer if available, confirm if it is a valid key press after de-bouncing, and update the key data into output data fifo if valid. the key press/release detection mechanism is listed below: 1. when the gpio is configured as keypad, the rows have internal "strong" pull-up and columns have internal "weak" pull-down. the initial states of the rows are logic high and the columns are logic low. 2. when a keypad is pressed, the corresponding row and column form a resistor voltage divider network. since the pull-up resistance of the row is stronger than the pull-down resistance of the column, the column is pulled to logic high. 3. once the column's state changes to logic high, the state machine initiates a key- scan cycle and drives the selected column to logic low. a low is detected on the !-6 /utput column -atrixkeypad
)nputrow
stmpe1801 keypad controller doc id 17884 rev 3 37/60 key-press row. this is because the row and column node of key press are shorted together. 4. the state machine continues to poll while the key is still pressed and is reinitialized once all the keys are released. the key detection sequence is described below: 1. the column outputs are initially not driven. 2. then the row inputs are checked for any special function keys. 3. next, the columns are checke d for any normal key presses. 4. with the internal pull-down resistor on the columns, the column senses a logic low. but when there is a normal key press, the pull up on the row and pull down on the column forms a resistor voltage divider. since the pull up resistor is sized much smaller than the pull down resistor, the voltage on the column is pulled to logic high state. 5. then only the configured columns that sensed a high are driven low in turn and check for normal key presses. this eliminates the need to drive columns that do not have any key press. this in turn reduces the switching amount and hence the reduction in noise and emi. also the 4 ma io during gpio mode is 1 ma in keypad mode.
keypad controller stmpe1801 38/60 doc id 17884 rev 3 11.1 keypad configurations the keypad controller supports the following types of keys: up to 10 columns * 8 rows matrix keys up to 8 special function keys up to 4 dedicated keys figure 8. keypad configuration !-6 stmpe1801 matrix keypad (10*8) output column 0 -9 input row 0-7 special function keys 10*8 (80) matrix keys 8 special function keys 0 dedicated keys
stmpe1801 keypad controller doc id 17884 rev 3 39/60 figure 9. keypad configurations !-6 stmpe1801 matrix keypad (10*4) output column 0-9 input row 0-7 special function keys 10*4 (40) matrix keys 4 special function keys 4 dedicated keys dedicated keys
keypad controller stmpe1801 40/60 doc id 17884 rev 3 11.2 keypad controller registers the mapping between the keypad controller (rows and columns) and the gpio is based on section 2.3 . table 14. keypad controller registers address register name description auto-increment (during sequential r/w) 30 kpc_row keypad row register yes 31 kpc_col_low keypad column register ye s 32 kpc_col_high yes 33 kpc_ctrl_low keypad control register ye s 34 kpc_ctrl_mid yes 35 kpc_ctrl_high yes 36 kpc_cmd key command register yes 37 kpc_combi_key_0 keypad combination key mask 0 yes 38 kpc_combi_key_1 keypad combination key mask 1 yes 39 kpc_combi_key_2 keypad combination key mask 2 yes 3a kpc_data_byte0 keypad data register ye s 3b kpc_data_byte1 yes 3c kpc_data_byte2 yes 3d kpc_data_byte3 yes 3e kpc_data_byte4 yes
stmpe1801 keypad controller doc id 17884 rev 3 41/60 kpc_row keypad controller row register address: 30 type: r/w reset: 0x00 description: keypad row scanning kpc_col_high keypad controller column (high) address: 32 type: r/w reset: 0x00 description: keypad column scanning register. 76543 2 1 0 input row 0 - 7 rw rw rw rw rw rw rw rw 00000 0 0 0 [7:0] input row 0 ? 7: ?1?: turn on scanning of the corresponding row .?0?: turn off 15 14 13 12 11 10 9 8 reserved output column 8 - 9 r r r r r r rw rw 00000 0 0 0 [15:10] reserved [9:8] output column 8-9: ?1?: turn on scanning of the corresponding column. ?0?: turn off
keypad controller stmpe1801 42/60 doc id 17884 rev 3 kpc_col_low keypad controller column (low) address: 31 type: r/w reset: 0x00 description: keypad column scanning register. kpc_ctrl_low keypad contro ller control (low) address: 33 type: r/w reset: 0x00 description: keypad control register. 76543 2 1 0 output column 0 - 7 rw rw rw rw rw rw rw rw 00000 0 0 0 [7:0] output column 0-7: ?1?: turn on scanning of the corresponding column. ?0?: turn off 76543 2 1 0 scan_count 0 ? 3 dkey 0 ? 3 rw rw rw rw rw rw rw rw 00000 0 0 0 [7:4] scan_count_0-3: number of key scanning cycles elapsed before a confirmed key data is updated into output data fifo (0-15 cycles) [3] dkey_3: set ?1? to use i nput row 3 as dedicated key [2] dkey_2: set ?1? to use i nput row 2 as dedicated key [1] dkey_1: set ?1? to use i nput row 1 as dedicated key [0] dkey_0: set ?1? to use i nput row 0 as dedicated key
stmpe1801 keypad controller doc id 17884 rev 3 43/60 kpc_ctrl_mid keypad cont roller control (mid) address: 34 type: r/w reset: 0x31 description: keypad control register. 76543 2 1 0 db[7:2] db0 rsvd rw rw rw rw rw rw r rw 01100 0 1 0 [7:1] db[7:2] and db0: db0 bit is fixed to ?1?. 10-127ms of de-bounce time de-bounce time range is from 10 ms to 127 ms with 50 ms as the default. [0] reserved
keypad controller stmpe1801 44/60 doc id 17884 rev 3 kpc_ctrl_high keypad c ontroller control (high) address: 35 type: r/w, r reset: 0x40 description: keypad data register. kpc_cmd keypad command register address: 36 type: r/w, r reset: 0x00 description: keypad command register. 76543 2 1 0 rsvd cmb_key reserved scan_freq rrwrrr r rw 01000 0 0 0 [7:4] reserved [6] cmb_key: combination key mode 1: and function for combination-key interrupt (default). 0: or function for combination-key interrupt. [5:2] reserved [1:0] scan_freq: scan frequency based on internal 32khz clock 00: 60 hz (default) 01: 30 hz 10: 15 hz 11: 275 hz 76543 2 1 0 rsvd rsvd rsvd rsvd rsvd rsvd kpc_lock scan r r r r r r rw rw 00000 0 0 [7:2] reserved [1] kpc_lock: keypad lock control bit 1: writing 1 to enter key pad lock state when the key press stops.
stmpe1801 keypad controller doc id 17884 rev 3 45/60 the kpc_lock bit is only used when a combination key is configured in the device. if there is no combination key programmed, then this bit is not used. this command is used in conjunction with the combination keys. after the device has entered the keypad lock state, all subsequent key presses are ignored until the combinational key(s) are detected. thereafter, the device exits the lock state, sets the combinational key wakeup status in the interrupt status register bit is[4] and sends out the interrupt if it was enabled. 0: writing 0 aborts the key lock writing a 0 to this bit cancels any earlier key lock execution command. if the device has already entered the lock state, writing 0 exits the lock state. this bit is readable by the host and the read status is described as follows: reading [1]: kpc lock execution is not completed. it is either waiting for the key press to stop to enter the lock state or it is already in the lock state. reading [0]: kpc is already not in lock st ate, and not waiting to enter lock state. [0]scan : 1: to start scanning 0: to stop note: all the key configurations and control must be completed before executing the scan command. any configuration and control chan ge while scan is active is not supported.
keypad controller stmpe1801 46/60 doc id 17884 rev 3 11.3 data registers the kpc_data register contains five bytes of information. the first three bytes store the key coordinates and status of any three keys from the normal key matrix, while the fourth byte stores the status of special function keys and the fifth byte consists of the status of dedicated keys. note: when accessing the kpc data fifo, it is mandatory to read all five bytes of kpc_data registers together consecutively.
stmpe1801 keypad controller doc id 17884 rev 3 47/60 kpc_data_byte0 keypad data byte 0 address: 3a type: r reset: 0xf8 description: keypad data register. kpc_data_byte1 keypad data byte 1 address: 3b type: r reset: 0xf8 description: keypad data register. 76543 2 1 0 up/dwn c3 c2 c1 c0 r2 r1 r0 rrrrr r r r 11111 0 0 0 [7] up/dwn: 0: key-down 1: key-up [6:3] c[3:0]: column number of key 1 (valid range: 0000-1001) 0x1111: no key [2:0] r[2:0]: row number of key 1 (valid range: 000-111) 76543 2 1 0 up/down c3 c2 c1 c0 r2 r1 r0 rrrrr r r r 11111 0 0 0 [7] up/down: 0: key-down 1: key-up [6:3] c[3:0]: column number of key 2 (valid range: 0000-1001) 0x1111: no key [2:0] row number of key 2 (valid range: 000-111)
keypad controller stmpe1801 48/60 doc id 17884 rev 3 kpc_data_byte2 keypad data byte 2 address: 3c type: r reset: 0xf8 description: keypad data register. kpc_data_byte3 keypad data byte 3 address: 3d type: r reset: 0xff description: keypad data register. 76543 2 1 0 up/down c3 c2 c1 c0 r2 r1 r0 rrrrr r r r 11111 0 0 0 [7] up/down: 0: key-down 1: key-up [6:3] c[3:0]: column number of key 3 (valid range: 0000-1001) 0x1111: no key [2:0] r[2:0]: row number of key 3 (valid range: 000-111) 76543 2 1 0 sf7 sf6 sf5 sf4 sf3 sf2 sf1 sf0 rrrrr r r r 11111 1 1 1 [7:0] sf[7:0]: 0: key-down 1: key-up
stmpe1801 keypad controller doc id 17884 rev 3 49/60 kpc_data_byte4 keypad data byte 4 address: 3e type: r reset: 0x0f description: keypad data register. 76543 2 1 0 reserved dedicated key 0 ? 3 rrrrr r r r 00001 1 1 1 [7:4] reserved [3:0] dedicated key [3:0]: 0: key down 1: key up
keypad controller stmpe1801 50/60 doc id 17884 rev 3 11.4 keypad combination key registers the 3 keypad controller mask registers contains the key combination to be used to wake up the kpc and send an interrupt to the host system. kpc_comb_key_n keypad co mbination [n = 0-2] address: 38, 39 type: r/w reset: 0xf8 description: keypad combination key mask registers. valid key press value must be entered. the valid range for stmpe1801 is 00 to 4f. any other value outside this range is not accepted and a none value of f8 is returned. 76543 2 1 0 c4 c3 c2 c1 c0 r2 r1 r0 rw rw rw rw rw rw rw rw 11111 0 0 0 [7:3] c[4:0]: column number of key n (valid range: 00000 ? 01001) [2:0] r[2:0]: row number of key n (valid range: 000 ? 111)
stmpe1801 keypad controller doc id 17884 rev 3 51/60 11.5 using the keypad controller it is not necessary to explicitly enable the internal pull-up, pull-down and direction by configuring the gpio control registers. once a gpio is enabled for the keypad function, its internal pull-up, pull-down and dire ction is controlled automatically. the scanning of row inputs should then be enabled for those gpio ports that are configured as keypad inputs by writing '1's to the corresponding bits in the kpc_row register. if any of the first four row inputs is to be used as dedicated key input, the corresponding bits in the kpc_ctrl_mid register should be set to '1'. the bits in the kpc_col_high and kpc_col_low registers should also be set correctly to enable the column output scanning for the corresponding gpio ports programmed as keypad outputs. the scan count and de-bounce count should also be programmed into the keypad control registers before enabling the keypad controller operation. to enable the keypad controller operation, the scan bit in the kpc_ctrl_low register must be set to '1'. the keypad controller operation can be disabled by setting the scan bit back to '0'. the kpc interrupt can be cleared upon status bit read, even if there is unread key-press in the kpc data register. it is the host respon sibility to read the kpc data register to access all key-press data. 11.5.1 ghost key handling the ghost key is inherent in keypad matrix that is not equipped with a diode at each of the keys. while it is not possible to avoid ghost key occurrence, the stmpe1801 allows the detection of possible ghost keys by the capab ility of detecting 3 simu ltaneous key-presses in the key matrix. the ghost key is only possible if 3 keys are pressed and held down together in a keypad matrix. if 3 keys are reported by the stmpe1801 keypad controller, it indicates a potential ghost key situation. the system may check for the possibility of a ghost key by analyzing the coordinates of the 3 keys. if the 3 keys form 3 corners of a rectangle, it could be a ghost key situation. a ghost key may also occur in the ?special function keys?. the keypad controller does not attempt to avoid the occurrence of ghost keys. however, the system should be aware that if more than one special fu nction key is reported, then ther e is a possibility of ghost keys. 11.5.2 key detection priority a dedicated key is always detected, if this is enabled. when a special function key is detected, the matrix key scanning on the same input line is disabled. up to 3 matrix keys can be detected. matrix keys that fall on activated special function keys are not counted. as a result of these priority rules, a matrix key is ignored by the keypad controller when the special function key on the same input line is detected, even if the matrix key is being pressed down before the special function key. hence, when a matrix is reported "key-down" and it is being held down while the correspondi ng special function is being pressed, a "no key" status is reported for the matrix key w hen the special function key is reported "key- down". if the matrix key is released while the special function key is still being held down, no "key-up" will be reported for the matrix key. on the other hand, if the matrix key is released after the special function key is reported "key-up", then a new "key-down" is reported for the matrix key, followed by "key-up".
keypad controller stmpe1801 52/60 doc id 17884 rev 3 11.5.3 keypad wakeup from hibernate mode the keypad controller is functional in hibernate mode as long as it is enabled before entering the hibernate mode. it will then wake th e system up into operational mode if a valid key press is detected. an asynchronous detection of the keypad column input activity is turned on during the hibernate mode. if any key activity is detected, the system wakes up into operational mode for the de-bouncing of the key press to take pl ace. if a valid key is detected, the system stays in operational mode; otherwise, the device goes back into hibernate mode. 11.5.4 keypad controller combination key interrupt the keypad controller (kpc) can be programmed to exit from hibernate mode if a unique combination keys is detected. these combination keys of up to 3 keys are specified in the kpc combination set 0-2 registers. there are 2 combination key operation modes. the modes can be set in the comb_key_mode in the kpc_ctrl_high register . in ?or? mode, the device exits from hibernate mode on any of the 3 keys specified in the kpc combination set 0-2 registers. in ?and? mode, the device exits from hibernate mo de only if all of the 3 keys are pressed. the sequence of the key pressed in not relevant as long as the 1-3 keys specified in the kpc_comb_key registers are detected, the kpc will exit from hibernate mode and interrupt the host. all the "active" keys must be pressed and held together, for the combi-key interrupt to be generated. if any other keys (beside those specified in the kpc_comb_key_ n registers) are pressed, it would be considered an invalid comb ination and no interrupt will be generated.
stmpe1801 miscellaneous features doc id 17884 rev 3 53/60 12 miscellaneous features 12.1 reset the stmpe1801 is equipped with an internal por circuit that holds the device in reset state, until the clock is steady and v cc input is valid. the por circuit is integrated with a filter with minimum 180 ns at 1.8 v v cc . the host system may choose to reset the stmpe1801 by asserting the rstb pin. the reset pin is also integrated with a filter of minimum 200 s duration and maximum 500 s duration.
package mechanical data stmpe1801 54/60 doc id 17884 rev 3 13 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 10. package outline for flip-chip csp 25 (2.03 x 2.03 mm) - 0.4 mm pitch
stmpe1801 package mechanical data doc id 17884 rev 3 55/60 figure 11. footprint recommendation table 15. package mechanical data for flip-chip csp 25 (2.03 x 2.03 mm) 0.4 mm pitch symbol millimeters min typ max a 0.55 0.605 0.660 a1 0.17 0.205 0.24 a2 0.38 0.4 0.42 b 0.215 0.255 0.295 d1.9722.03 d1 - 1.6 - e1.9722.03 e1 - 1.6 - e 0.36 0.4 0.44 f 0.190 0.200 0.210 ccc - 0.05 0.05
package mechanical data stmpe1801 56/60 doc id 17884 rev 3 figure 12. device marking figure 13. carrier tape information 1. pin a1 is at top left corner based on above tape orientation. !-6 ' )dentificationfor (alogenfree 6,. 977 )dentificationfor traceabledatecode )dentificationfor devicefront end andback endplant
stmpe1801 package mechanical data doc id 17884 rev 3 57/60 table 16. carrier tape specifications symbol millimeters min typ max a0 2.06 2.11 2.16 b0 2.06 2.11 2.16 k0 0.64 0.69 0.74 f 3.45 3.50 3.55 w 7.90 8.00 8.30 p2 1.95 2.00 2.05 p0 3.90 4.00 4.10 10p0 39.80 40.00 40.20 d0 1.50 1.55 1.60 t 0.185 0.200 0.215 p 3.90 4.00 4.10 table 17. tape width (millimeters) tape width a n w1 w2 w3 max min max max min max 8 180 60 8,4 14.4 7.9 10.9
package mechanical data stmpe1801 58/60 doc id 17884 rev 3 figure 14. reel drawing (front) figure 15. reel drawing (back)
stmpe1801 revision history doc id 17884 rev 3 59/60 14 revision history table 18. document revision history date revision changes 15-nov-2010 1 initial release. 13-dec-2010 2 updated: figure 12 and added footnote related to figure 13 . 09-mar-2011 3 updated: pin a1 function in ta bl e 2 and section 12.1 .
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